Intel is set to roll out its latest generation of processors this spring despite a minor setback affecting ultra depression-voltage models -- the ones destined for super slim notebooks. Past normal standards, the launch should mark a new "tick" in the company's product roadmap, only Intel is going beyond just shrinking the current 32nm Sandy Bridge processor by introducing some fundamental advancements along with its new 22nm process.

For those unfamiliar, Intel follows a "tick tock" model for its processor upgrade wheel. With every "tick" the company moves to a smaller manufacturing procedure, from 32nm to 22nm in this case, dramatically increasing transistor density while enhancing performance and free energy efficiency of the electric current microarchitecture. Then, with an alternating "tock" cycle Intel introduces a new processor microarchitecture.

Ivy Bridge includes manufacturing and subsystem improvements. It is a compress of Sandy Bridge and is besides the first to us Intel's Tri-Gate transistors, which utilize a nonplanar architecture to cram more transistors into less space, therefore consuming less power or delivering more performance within the same power envelope.

There's been quite a chip of information on Ivy Bridge going effectually ever since Intel detailed the architecture belatedly concluding twelvemonth. We'll recap some of the major changes and applied implications, while besides bringing yous upward to speed on the latest developments, including expected launch lineup and specs.

Tri-Gate transistors = Improved effiency, performance

Unlike conventional planar transistors that lay flat, Ivy Span's Tri-Gate transistors use a three-dimensional fin that stands vertically from the silicon substrate. This presents several benefits. For starters, Intel tin cram more transistors into less space, which will be incredibly valuable as fabrication tech shrinks to 22nm and beyond.

In addition, the new design allows for essentially three times the surface area for electrons to travel when the transistor is in the 'on' state, which paves the manner for increased performance.

Transistors acquit an electrical signal while gates control that menstruation by turning the current on and off. Whereas in a typical transistor only the pocket-size layer between the channel and the gate becomes active when the transistor is switched on, Intel's Tri-Gate transistor creates a three-sided silicon fin that the gate wraps around, increasing the surface surface area where electrical current actually flows. The video below does a meliorate task explaining this.

This design also maximizes transistor switching performance between on and off states and decreases ability-wasting leakage.

Intel summarizes the practical implications by proverb the 22nm 3D Tri-Gate transistors provide upwardly to a 37% performance increase at low operating voltages versus Intel's 32nm planar transistors -- a big bargain for Cantlet and ULV chips -- or close to twenty% at 1V for higher end desktop and mobile parts.

Alternatively, the new 22nm Tri-Gate transistors can swallow less than half the ability when at the aforementioned operation level as 2D planar transistors on 32nm chips.

Intel has besides mentioned the possibility to have multiple fins standing vertically from the silicon substrate and connected together, as shown to the right, to increase total drive strength of the transistor for college performance. They haven't discussed this in detail just nosotros presume Intel could use it to more than finely tune its 22nm process in higher finish products, or use information technology as a fail-safe method to amend yields of individual dies.

The new 22nm Tri-Gate wafers shouldn't be much more expensive to produce, either. Compared to a hypothetical Intel 22nm planar process, the 3D Tri-Gate procedure should just add some other 2-3% to the total price, co-ordinate to Intel's own estimates.

Other architecture changes

Besides the new transistor blueprint at that place are no major changes in the Ivy Span architecture compared to Sandy Bridge. Information technology continues the two-scrap platform partitioning (CPU + PCH) and is backwards compatible with existing LGA-1155 motherboards, although in that location volition exist new chipsets to enable new features.

The central portion of the die has four x86-64 cores with 256 KB dedicated L2 cache each and a shared 8 MB L3 enshroud. To each side of this central portion is the arrangement agent and the graphics core.

All these components are jump by a ring-omnibus that transports information between them. The system agent has interfaces for the dual-channel DDR3 integrated memory controller, the PCI-Express controller (supporting 16 PCIe 3.0 lanes), the DMI chipset bus, a display controller, and FDI link to the PCH.

Graphics

But there are also a few tweaks here and there. First and foremost the graphics core has been completely redesigned and now supports OpenCL one.ane, DirectX 11 and OpenGL iii.1. This will finally bring the Intel integrated GPU to feature parity with AMD's. Intel too added a graphics-specific L3 cache, three display outputs (up from two in Sandy Span), amend anisotropic filtering, more than shaders or execution units (either 8 or 16 EUs in Ivy Span depending on the GPU versus six or 12 in Sandy Span), and a few other enhancements.

Ivy Bridge likewise profoundly improves Intel Quick Sync Video, the scrap giant'due south transcoding technology. All told, the stop effect is up to a threescore% increase in GPU performance over Sandy Span'due south integrated GPU.

Hyper-Threading and CPU instruction prepare changes On the CPU side there are some changes in the way resource allocation for HyperThreading queue takes place. Ivy Bridge will dynamically allocate resource to threads and so that if there is only a single thread agile, all resource volition be dedicated to that thread rather than some going unused as with SB's static resource allotment.

There's a new random number generation procedure that improves security, a power direction feature that offers more flexibility in setting a system'southward thermal envelope (more on this next), and memory and string performance enhancements. Ivy Span likewise reportedly allows for more dynamic overclocking.

On the next two pages: Ivy Bridge's power optimizations & CPU and chipset confirmed launch line-ups.